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All-In-Wonder 9500
amd
discrete
Released 2002-07-01
All-In-Wonder 9500
Architecture:
R300
• Generation: All-In-Wonder(9000)
Configure in Manual PC Builder
VRAM Capacity
0.128 GB
DDR
FP32 Compute
Standard
Single Precision
Thermal TDP
Standard
Max Sustained Power
Memory Bandwidth
8.64 GB/s
128-bit Bus
Silicon & Compute Pipeline
Microarchitecture
R300
Generation Series
All-In-Wonder(9000)
Process Node
150 nm
Die Size
215 mm²
Transistor Count
0.11 Billion
Shading Units / CUDA Cores
N/A
Clock Speeds & Bus Interface
Base Clock Speed
277 MHz
Boost Clock Speed
277 MHz
Memory Clock
270 MHz
Memory Bus Width
128-bit
Bus Interface
AGP 8x
Supported APIs
DirectX 9.0
Data Source:
open-gpu-db
(upstream: dbgpu). Licensed under ODbL Open Data.
Verify Upstream Record